View PCM4104-EP-15_9064710.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features applications pcm4104-ep sbas419 ? june 2007 high-performance, 24-bit, 216-khz sampling, four-channel audio digital-to-analog converter ? 256 steps with 0.5 db per step controlled baseline output phase inversion (software mode only) ? one assembly/test site, one fabrication zero data mute (software mode only) site audio serial port extended temperature performance of ?40 c ? supports left-justified, right-justified, to 85 c i 2 s?, and tdm data formats enhanced diminishing manufacturing sources ? accepts 16-, 18-, 20-, and 24-bit two's (dms) support complement pcm audio data enhanced product-change notification standalone or software-controlled qualification pedigree (1) configuration modes four high-performance, multi-level, four-wire serial peripheral interface (spi?) delta-sigma digital-to-analog converters port provides control register access in software mode differential voltage outputs power supplies: 5 v analog, 3.3 v digital ? full-scale output (differential): 6.15 v pp power dissipation supports sampling frequencies up to 216 khz ? 203 mw typical with f s = 48 khz typical dynamic performance (24-bit data) ? 220 mw typical with f s = 96 khz ? dynamic range (a-weighted): 118 db ? 236 mw typical with f s = 192 khz ? thd+n: ?100 db power-down modes linear phase, 8 oversampling digital interpolation filter small 48-lead tqfp package digital de-emphasis filters for 32-khz, 44.1-khz, and 48-khz sampling rates digital mixing consoles soft mute function digital audio workstations ? all-channel mute via the mute input pin digital audio effects processors ? per-channel mute available in software broadcast studio equipment mode surround-sound processors digital attenuation (software mode only) high-end a/v receivers ? attenuation range: 0 db to ?119.5 db (1) component qualification in accordance with jedec and industry standards to ensure reliable operation over an extended temperature range. this includes, but is not limited to, highly accelerated stress test (hast) or biased 85/85, temperature cycle, autoclave or unbiased hast, electromigration, bond intermetallic life, and mold compound life. such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www.ti.com
description absolute maximum ratings pcm4104-ep sbas419 ? june 2007 the pcm4104 is a high-performance, four-channel digital-to-analog (d/a) converter designed for use in professional audio applications. the pcm4104 supports 16- to 24-bit linear pcm input data, with sampling frequencies up to 216 khz. the pcm4104 features lower power consumption than most comparable stereo audio d/a converters, making it ideal for use in high channel count applications by lowering the overall power budget required for the d/a conversion subsystem. the pcm4104 features delta-sigma architecture, employing a high-performance multi-level modulator combined with a switched capacitor output filter. this architecture yields lower out-of-band noise and a high tolerance to system clock phase jitter. differential voltage outputs are provided for each channel and are well-suited to high-performance audio applications. the differential outputs are easily converted to a single-ended output using an external op amp ic. the pcm4104 includes a flexible audio serial port interface, which supports standard and time division multiplexed (tdm) formats. support for tdm formats simplifies interfacing to dsp serial ports, while supporting a cascade connection for two pcm4104 devices. in addition, the pcm4104 offers two configuration modes: standalone and software-controlled. the standalone mode provides dedicated control pins for configuring a subset of the available pcm4104 functions, while software mode utilizes a serial peripheral interface (spi) port for accessing the complete feature set via internal control registers. the pcm4104 operates from a 5-v analog power supply and a 3.3-v digital power supply. the digital i/o is compatible with 3.3-v logic families. the pcm4104 is available in a tqfp-48 package. ordering information (1) specified package- package package ordering transport product temperature lead designator (2) marking number media, quantity range pcm4104 tqfp-48 pfb ?40 c to 85 c pcm4104ep pcm4104ipfbrep tape and reel, 2000 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. over operating free-air temperature range (unless otherwise noted) (1) pcm4104 unit v cc 6.0 v supply voltage v dd 3.6 v ground voltage difference any agnd-to-agnd and agnd-to-dgnd 0.1 v fs0, fs1, fmt0, fmt1, fmt2, cdout, cdin, cclk, cs, digital input voltage data0, data1, bck, lrck, scki, sub, dem0, dem1, mute, ?0.3 to (v dd + 0.3) v rst, mode input current (any pin except supplies) 10 ma operating temperature range ?40 to 85 c storage temperature range, t stg ?65 to 150 c (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 2 submit documentation feedback www.ti.com
electrical characteristics pcm4104-ep sbas419 ? june 2007 all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, (unless otherwise noted) and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. pcm4104 parameter conditions units min typ max resolution 24 bits data format audio data formats left or right justified, i 2 s, and tdm audio data word length 16 24 bits binary data format two?s complement binary, msb first clock rates and timing single rate sampling mode 6.144 36.864 system clock frequency f sclk dual rate sampling mode 13.824 36.864 mhz quad rate sampling mode 13.824 36.864 single rate sampling mode 24 54 sampling frequency f s dual rate sampling mode 54 108 khz quad rate sampling mode 108 216 spi port data clock f cclk 24 mhz spi port data clock high time t cclkh 15 ns spi port data clock low time t cclkl 15 ns digital input/output v ih 2.0 v input logic level v il 0.8 v i ih v in = 2.64 v (for ?40 c to 85 c) 1 10 a input logic current i il v in = 0.66 v (for ?40 c to 85 c) 1 ?10 a v oh i oh = ?2 ma (for ?40 c to 85 c) 2.4 v output logic level v ol i ol = +2 ma (for ?40 c to 85 c) 0.4 v analog outputs full-scale output voltage, differential r l = 600 w 6.15 v pp bipolar zero voltage 2.5 v output impedance 5 ohms switched capacitor filter frequency f = 20 khz, all sampling modes ?0.2 db response gain error 0.5 % fsr gain mismatch, channel-to-channel 0.6 % fsr bipolar zero error 1 mv v com 1 and v com 2 output voltage v cc = 5 v 2.5 v v com 1 and v com 2 output current 200 a 3 submit documentation feedback www.ti.com
pcm4104-ep sbas419 ? june 2007 electrical characteristics (continued) all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, (unless otherwise noted) and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. pcm4104 parameter conditions units min typ max dynamic performance with 24-bit data (1) f s = 48 khz f = 1 khz at 0 dbfs ?100 ?94 total harmonic distortion + thd+n f = 1 khz at 0 dbfs (for ?40 c to 85 c) -91 db noise f = 1 khz at ?60 dbfs ?56 f = 1 khz at ?60 dbfs 112 118 db dynamic range, a-weighted f = 1 khz at ?60 dbfs (for ?40c to 85 c) 109 db idle channel snr, a-weighted all zero input data 119 db idle channel snr, unweighted all zero input data 116 db f = 1 khz at 0 dbfs for active channel 100 110 db channel separation f = 1 khz at 0 dbfs for active channel (for 98 db ?40c to 85 c) f s = 96 khz f = 1 khz at 0 dbfs, ?100 bw = 10 hz to 40 khz total harmonic distortion + thd+n db noise f = 1 khz at ?60 dbfs, ?53 bw = 10 hz to 40 khz dynamic range, a-weighted f = 1 khz at ?60 dbfs 118 db idle channel snr, a-weighted all zero input data 119 db idle channel snr, unweighted all zero input data, bw = 10 hz to 40 khz 113 db channel separation f = 1 khz at 0 dbfs for active channel 110 db f s = 192 khz f = 1 khz at 0 dbfs, ?97 bw = 10 hz to 40 khz total harmonic distortion + thd+n db noise f = 1 khz at ?60 dbfs, ?53 bw = 10 hz to 40 khz dynamic range, a-weighted f = 1 khz at ?60 dbfs 118 db idle channel snr, a-weighted all zero input data 118 db idle channel snr, unweighted all zero input data, bw = 10 hz to 40 khz 113 db channel separation f = 1 khz at 0 dbfs for active channel 110 db dynamic performance with 16-bit data f s = 44.1 khz f = 1 khz at 0 dbfs ?92 total harmonic distortion + thd+n db noise f = 1 khz at ?60 dbfs ?33 dynamic range, a-weighted f = 1 khz at ?60 dbfs 96 db idle channel snr, a-weighted (2) all zero input data 118 db idle channel snr, unweighted (2) all zero input data 115 db digital filters (1) dynamic performance parameters are measured using an audio precision system two cascade or cascade plus test system. input data word length is 24 bits with triangular pdf dither added for dynamic range and thd+n tests. idle channel snr is measured with both the soft and zero data mute functions disabled and 0% full?scale input data with no dither applied. the measurement bandwidth is limited by using the audio precision 10 hz high?pass filter in combination with either the aes17 20 khz low-pass filter or aes17 40 khz low-pass filter. all a-weighted measurements are performed using the audio precision a-weighting filter in combination with either the 22 khz or 80 khz low-pass filter. measurement mode is set to rms for all parameters. the average measurement mode will yield better typical performance numbers. (2) idle channel snr is not limited by word length. 4 submit documentation feedback www.ti.com
pcm4104-ep sbas419 ? june 2007 electrical characteristics (continued) all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, (unless otherwise noted) and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. pcm4104 parameter conditions units min typ max 0.002 db 0.454f s hz passband ?3 db 0.487f s hz stop band 0.546f s hz passband ripple 0.002 db 0.546fs ?75 db stopband attenuation 0.567fs ?82 db group delay 29/f s sec de-emphasis filter error 0.1 db power supply supply range analog supply, v cc 4.75 5.0 5.25 v digital supply, v dd 3.0 3.3 3.6 v power down current v cc = 5 v, vdd = 3.3 v power-down supply current, i cc + i dd rst = low, system and audio clocks off 1 ma quiescent current system and audio clocks applied, all 0s data v cc = 5 v, f s = 48 khz ( for ?40 c to 32 45 85 c) analog supply, i cc ma v cc = 5 v, f s = 96 khz 32 v cc = 5 v, f s = 192 khz 32 v dd = 3.3 v, f s = 48 khz ( for ?40 c to 13 17 85 c) digital supply, i dd ma v dd = 3.3 v, f s = 96 khz 18 v dd = 3.3 v, f s = 192 khz 23 v cc = 5 v, v dd = 3.3 v f s = 48 khz ( for ?40 c to 85 c) 203 286 total power dissipation f s = 96 khz 220 mw f s = 192 khz 236 5 submit documentation feedback www.ti.com
pin assignments pcm4104-ep sbas419 ? june 2007 terminal functions terminal i/o description name no. v out 1+ 1 output channel 1 analog output, noninverted v out 1? 2 output channel 1 analog output, inverted agnd1 3 ground analog ground v ref 1? 4 input channel 1 low reference voltage; connect to agnd v ref 1+ 5 input channel 1 high reference voltage; connect to v cc nc 6 no internal connection nc 7 no internal connection mode 8 input operating mode (0 = standalone, 1= software controlled) rst 9 input reset/power down (active low) mute 10 input all-channel soft mute (active high) dem1 11 input digital de-emphasis filter configuration dem0 12 input digital de-emphasis filter configuration sub 13 input sub-frame assignment (tdm formats only) scki 14 input system clock bck 15 input audio bit (or data) clock lrck 16 input audio left/right (or word) clock audio data for channels 1 and 2 (i 2 s, left/right justified formats) or audio data for channels data0 17 input 1 through 4 for tdm formats data1 18 input audio data for channels 3 and 4 (i 2 s, left/right justified formats) 6 submit documentation feedback www.ti.com tqfp p ackage (t op view) 36 35 34 33 32 31 30 29 28 27 26 25 v out 4+ v out 4 - agnd2 v ref 4 - v ref 4+ nc nc fs1 fs0 fmt2 fmt1 fmt0 v com 1 v out 2+ v out 2 - v cc 1 v ref 2+ v ref 2 - v ref 3 - v ref 3+ v cc 2 v out 3 - v out 3+ v com 2 sub scki bck lrck data0 data1 v dd dgnd cs cclk cdin cdout 12 3 4 5 6 7 8 9 10 11 12 v out 1+ v out 1 - agnd1 v ref 1 - v ref 1+ nc nc mode rst mute dem1 dem0 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 pcm4104
pcm4104-ep sbas419 ? june 2007 pin assignments (continued) terminal functions (continued) terminal i/o description name no. v dd 19 power digital power supply, 3.3 v dgnd 20 ground digital ground cs 21 input serial peripheral interface (spi) chip select (active low) cclk 22 input serial peripheral interface (spi) data clock cdin 23 input serial peripheral interface (spi) data input cdout 24 output serial peripheral interface (spi) data output fmt0 25 input audio data format configuration fmt1 26 input audio data format configuration fmt2 27 input audio data format configuration fs0 28 input sampling mode configuration fs1 29 input sampling mode configuration nc 30 no internal connection nc 31 no internal connection v ref 4+ 32 input channel 4 high reference voltage; connect to v cc v ref 4? 33 input channel 4 low reference voltage; connect to agnd agnd2 34 ground analog ground v out 4? 35 output channel 4 analog output, inverted v out 4+ 36 output channel 4 analog output, noninverted v com 2 37 output dc common-mode voltage for channels 3 and 4, 2.5 v nominal v out 3+ 38 output channel 3 analog output, noninverted v out 3? 39 output channel 3 analog output, inverted v cc 2 40 power analog power supply, 5 v v ref 3+ 41 input channel 3 high reference voltage; connect to v cc v ref 3? 42 input channel 3 low reference voltage; connect to agnd v ref 2? 43 input channel 2 low reference voltage; connect to agnd v ref 2+ 44 input channel 2 high reference voltage; connect to v cc v cc 1 45 power analog power supply, 5 v v out 2? 46 output channel 2 analog output, inverted v out 2+ 47 output channel 2 analog output, noninverted v com 1 48 output dc common-mode voltage for channels 1 and 2, 2.5 v nominal 7 submit documentation feedback www.ti.com
typical characteristics pcm4104-ep sbas419 ? june 2007 all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. 8 submit documentation feedback fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 96khz f in = 1khz 0dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 96khz f in = 1khz - 20dbfs amplitude 24?bit data www.ti.com fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 48khz f in = 1khz 0dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 48khz f in = 1khz - 20dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 48khz idle channel input 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 48khz f in = 1khz - 60dbfs amplitude 24?bit data
pcm4104-ep sbas419 ? june 2007 typical characteristics (continued) all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. 9 submit documentation feedback fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 96khz f in = 1khz - 60dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 96khz idle channel input 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 192khz f in = 1khz 0dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 192khz f in = 1khz - 20dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 192khz f in = 1khz - 60dbfs amplitude 24?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 40k f s = 192khz idle channel input 24?bit data www.ti.com
pcm4104-ep sbas419 ? june 2007 typical characteristics (continued) all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. 10 submit documentation feedback fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 44.1khz f in = 1khz 0dbfs amplitude 16?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 44.1khz f in = 1khz - 20dbfs amplitude 16?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 44.1khz f in = 1khz - 60dbfs amplitude 16?bit data fft plot frequency (hz) amplitude (db) 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 - 160 1k 100 20 10k 20k f s = 44.1khz idle channel input 16?bit data thd+n vs amplitude amplitude (dbfs) thd+n (db) - 80 - 85 - 90 - 95 - 100 - 105 - 110 - 115 - 120 - 150 - 140 - 130 - 120 - 110 - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 f s = 48khz f in = 1khz 24?bit data thd+n vs amplitude amplitude (dbfs) thd+n (db) - 80 - 85 - 90 - 95 - 100 - 105 - 110 - 115 - 120 - 150 - 140 - 130 - 120 - 110 - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 f s = 96khz f in = 1khz 24?bit data www.ti.com
pcm4104-ep sbas419 ? june 2007 typical characteristics (continued) all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. 11 submit documentation feedback thd+n vs amplitude amplitude (dbfs) thd+n (db) - 80 - 85 - 90 - 95 - 100 - 105 - 110 - 115 - 120 - 150 - 140 - 130 - 120 - 110 - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 f s = 192khz f in = 1khz 24?bit data thd+n vs amplitude amplitude (dbfs) thd+n (db) - 80 - 85 - 90 - 95 - 100 - 105 - 110 - 115 - 120 - 150 - 140 - 130 - 120 - 110 - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 f s = 44.1khz f in = 1khz 16?bit data 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 frequency response 0 1 2 3 4 frequency (x f s ) amplitude (db) 0.003 0.002 0.001 0 - 0.001 - 0.002 - 0.003 passband ripple 0 0.1 0.2 0.3 0.4 0.5 frequency (x f s ) amplitude (db) 0.0 - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10.0 de?emphasis filter response (f s = 32khz) 0 2 4 6 8 10 12 14 frequency (khz) level (db) 0.5 0.4 0.3 0.2 0.1 0.0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 de?emphasis error (f s = 32khz) 0 2 4 6 8 10 12 14 frequency (khz) error (db) www.ti.com
pcm4104-ep sbas419 ? june 2007 typical characteristics (continued) all parameters are specified at t a = 25 c with v cc = 5 v, v dd = 3.3 v, and a measurement bandwidth from 10 hz to 20 khz, unless otherwise noted. system clock frequency is equal to 256f s for single and dual rate sampling modes, and 128f s for quad rate sampling mode. 12 submit documentation feedback www.ti.com 0.0 - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10.0 de?emphasis filter response (f s = 44.1khz) 0 2 4 6 8 10 12 14 16 18 20 frequency (khz) level (db) 0.5 0.4 0.3 0.2 0.1 0.0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 de?emphasis error (f s = 44.1khz) 0 2 4 6 8 10 12 14 16 18 20 frequency (khz) error (db) 0.0 - 1.0 - 2.0 - 3.0 - 4.0 - 5.0 - 6.0 - 7.0 - 8.0 - 9.0 - 10.0 de? emphasis filter response (f s = 48khz) 0 2 4 6 8 10 12 14 16 18 22 frequency (khz) level (db) 0.5 0.4 0.3 0.2 0.1 0.0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 de? emphasis error (f s = 48khz) 0 2 4 6 8 10 12 14 16 18 22 frequency (khz) error (db)
product overview pcm4104-ep sbas419 ? june 2007 the pcm4104 is a high-performance, four-channel d/a converter designed for professional audio systems. the pcm4104 supports 16- to 24-bit linear pcm input data and sampling frequencies up to 216 khz. the pcm4104 utilizes an 8 oversampling digital interpolation filter, followed by a multi-level delta-sigma modulator with a single pole switched capacitor output filter. this architecture provides excellent dynamic and sonic performance, as well as high tolerance to clock phase jitter. functional block diagrams, showing both standalone and software modes, are shown in figure 1 and figure 2 . the pcm4104 incorporates a flexible audio serial port, which accepts 16- to 24-bit pcm audio data in both standard audio formats (left justified, right justified, and philips i 2 s) and tdm data formats. the tdm formats are especially useful for interfacing to the synchronous serial ports of digital signal processors. the tdm formats support daisy-chaining of two pcm4104 devices on a single three-wire serial interface (for sampling frequencies up to 108 khz), forming a high-performance eight-channel d/a conversion system. the pcm4104 offers two modes for configuration control: software and standalone. software mode makes use of a four-wire spi port to access internal control registers, allowing configuration of the full pcm4104 feature set. standalone mode offers a more limited subset of the functions available in software mode, while allowing for a simplified pin-programmed configuration mode. figure 1. functional block diagram for standalone mode 13 submit documentation feedback www.ti.com digital filtering and functions audio serial port control v ref 1+ v out 1+ v out 1 - v ref 1 - v ref 2+ v out 2+ v out 2 - v ref 2 - v com 1 v ref 3+ v out 3+ v out 3 - v ref 3 - v ref 4+ v out 4+ v out 4 - v ref 4 - v com 2 digital power analog power system clock and timing v cc 1 agnd1 v cc2 1 agnd2 v dd dgnd d/a converter and output filter d/a converter and output filter d/a converter and output filter d/a converter and output filter lrck bck data0 data1 scki rst mute dem0 dem1 sub fmt0 fmt1 fmt2 fs0 fs1 mode
analog outputs pcm4104-ep sbas419 ? june 2007 product overview (continued) figure 2. pcm4104 functional block diagram for software mode the pcm4104 provides four differential voltage outputs, corresponding to audio channels 1 through 4. v out 1+ (pin 1) and v out 1? (pin 2) correspond to channel 1. v out 2+ (pin 47) and v out 2? (pin 46) correspond to channel 2. v out 3+ (pin 38) and v out 3? (pin 39) correspond to channel 3. v out 4+ (pin 36) and v out 4? (pin 35) correspond to channel 4. each differential output is typically capable of providing 6.15-v full-scale (differential) into a 600 w output load. the output pins are internally biased to the common-mode (or bipolar zero) voltage, which is nominally v cc /2. the output section of each d/a converter channel includes a single-pole, switched capacitor low-pass filter circuit. the switched capacitor filter response tracks with the sampling frequency of the d/a converter and provides attenuation of the out-of-band noise produced by the delta-sigma modulator. an external two-pole continuous time filter is recommended to further reduce the out-of-band noise energy and to band limit the output spectrum to frequencies suitable for audio reproduction. refer to the applications information section of this data sheet for recommended output filter circuits. 14 submit documentation feedback www.ti.com lrck bck data0 data1 scki rst mute sub cs cclk cdin cdout mode v ref 1+ v out 1+ v out 1 - v ref 1 - v ref 2+ v out 2+ v out 2 - v ref 2 - v com 1 v ref 3+ v out 3+ v out 3 - v ref 3 - v ref 4+ v out 4+ v out 4 - v ref 4 - v com 2 digital filtering and functions audio serial port control and spi port digital power analog power system clock and timing v cc 1 agnd1 v cc2 1 agnd2 v dd dgnd v dd d/a converter and output filter d/a converter and output filter d/a converter and output filter d/a converter and output filter
voltage references sampling modes pcm4104-ep sbas419 ? june 2007 product overview (continued) the pcm4104 includes high and low reference pins for each output channel. v ref 1+ (pin 5) and v ref 1? (pin 4) correspond to channel 1. v ref 2+ (pin 44) and v ref 2? (pin 43) correspond to channel 2. v ref 3+ (pin 41) and v ref 3? (pin 42) correspond to channel 3. v ref 4+ (pin 32) and v ref 4? (pin 33) correspond to channel 4. the high reference (+) pin may be connected to the corresponding v cc supply or an external 5-v reference, while the low reference (?) pin is connected to analog ground. a 0.01- f bypass capacitor should be placed between the corresponding high and low reference pins. an x7r ceramic chip capacitor is recommended for this purpose. in some cases, a larger capacitor may need to be placed in parallel with the 0.01- f capacitor, with the value of the larger capacitor being dependent upon the low-frequency power-supply noise present in the system. typical values may range from 1 f to 10 f. low esr tantalum or multilayer ceramic chip capacitors are recommended. figure 3 illustrates the recommended connections for the reference pins. figure 3. recommended connections for voltage reference and common-mode output pins in addition to the reference pins, there are two common-mode voltage output pins, v com 1 (pin 48) and v com 2 (pin 37). these pins are nominally set to a value equal to v cc /2 by internal voltage dividers. the v com 1 pin is common to both channels 1 and 2, while the v com 2 pin is common to channels 3 and 4. a 0.1- f x7r ceramic chip capacitor should be connected between the common-mode output pin and analog ground. the common-mode outputs are used primarily to bias external output circuitry. the pcm4104 can operate in one of three sampling modes: single rate, dual rate, or quad rate. sampling modes are selected by using the fs[1:0] bits in control register 6 in software mode, or by using the fs0 (pin 28) and fs1 (pin 29) inputs in standalone mode. the single rate mode allows sampling frequencies up to and including 54 khz. the d/a converter performs 128 oversampling of the input data in single rate mode. the dual rate mode allows sampling frequencies greater than 54 khz, up to and including 108 khz. the d/a converter performs 64 oversampling of the input data in dual rate mode. the quad rate mode allows sampling frequencies greater than 108 khz, up to and including 216 khz. the d/a converter performs 32 oversampling of the input data in quad rate mode. refer to table 1 for examples of system clock requirements for common sampling frequencies. 15 submit documentation feedback www.ti.com (1) capacitor(s) required for each of the four reference pai rs. v ref + (1) v com 1 0.01 m f 0.1 m f 0.1 m f 0.1 m f to 10 m f v cc v com 2 v ref - (1)
system clock requirements pcm4104-ep sbas419 ? june 2007 product overview (continued) the pcm4104 requires a system clock, applied at the scki (pin 14) input. the system clock operates at an integer multiple of the input sampling frequency, or f s . the multiples supported include 128f s , 192f s , 256f s , 384f s , 512f s , or 768f s . the system clock frequency is dependent upon the sampling mode. table 1 shows the required system clock frequencies for common audio sampling frequencies. figure 4 shows the system clock timing requirements. although the architecture of the pcm4104 is tolerant to phase jitter on the system clock, it is recommended that the user provide a low jitter clock (100 picoseconds or less) for optimal performance. table 1. sampling modes and system clock frequencies for common audio sampling rates sampling system clock frequency (mhz) sampling frequency, f s mode 128f s 192f s 256f s 384f s 512f s 768f s (khz) single rate 32 n/a n/a 8.192 12.288 16.384 24.576 single rate 44.1 n/a n/a 11.2896 16.9344 22.5792 33.8688 single rate 48 n/a n/a 12.288 18.432 24.576 36.864 dual rate 88.2 n/a n/a 22.5792 33.8688 n/a n/a dual rate 96 n/a n/a 24.576 36.864 n/a n/a quad rate 176.4 22.5792 33.8688 n/a n/a n/a n/a quad rate 192 24.576 36.864 n/a n/a n/a n/a figure 4. system clock timing requirements 16 submit documentation feedback www.ti.com scki t scki t sckih t sckil parameter description min max units system clock period 26 ns t sckih system clock high pulse time 12 ns t sckil system clock low pulse time 12 ns t scki
reset operation pcm4104-ep sbas419 ? june 2007 the pcm4104 includes three reset functions: power-on, external, and software-controlled. this section describes each of the three reset functions. on power up, the internal reset signal is forced low, forcing the pcm4104 into a reset state. the power-on reset circuit monitors the v dd , v cc 1, and v cc 2 power supplies. when v dd exceeds 2 v (margin of error is 400 mv) and v cc 1 and v cc 2 exceed 4 v (margin of error is 400 mv), the internal reset signal is forced high. the pcm4104 then waits for the system clock input (scki) to become active. once the system clock has been detected, the initialization sequence begins. the initialization sequence requires 1024 system clock periods for completion. when the initialization sequence is completed, the pcm4104 is ready to accept audio data at the audio serial port. figure 5 shows the power-on reset sequence timing. if the pcm4104 is configured for software mode control via the spi port, all control registers will be reset to their default state during the initialization sequence. in both standalone and software modes, the analog outputs for all four channels are muted during the reset and initialization sequence. while in mute state, the analog output pins are driven to the bipolar zero voltage, or v cc /2. the user may force a reset initialization sequence at any time while the system clock input is active by utilizing the rst input (pin 9). the rst input is active low, and requires a minimum low pulse width of 40 nanoseconds. the low-to-high transition of the applied reset signal will force an initialization sequence to begin. as in the case of the power-on reset, the initialization sequence requires 1024 system clock periods for completion. figure 6 illustrates the reset sequence initiated when using the rst input. a reset initialization sequence is available in software mode, using the rst bit in control register 6. the rst bit is active high. when rst is set to 1, a reset sequence is initiated in the same fashion as an external reset applied at the rst input. figure 7 shows the state of the analog outputs for the pcm4104 before, during and after the reset operations. figure 5. power-up reset timing 17 submit documentation feedback www.ti.com 1024 system clock periods required for initialization system clock indeterminate or inactive scki ~ 2.0v ~ 4.0v 0v 0v 0v 0v internal reset v cc 1 v cc 2 v dd
power-down operation pcm4104-ep sbas419 ? june 2007 figure 6. external reset timing figure 7. analog output state for reset operations the pcm4104 can be forced to a power-down state by applying a low level to the rst input for a minimum of 65,536 system clock cycles. in power-down mode, all internal clocks are stopped, and analog outputs are set to a high-impedance state. the system clock can then be removed to conserve additional power. in the case of system clock restart when exiting the power-down state, the clock should be restarted prior to a low-to-high transition of the reset signal at the rst input. the low-to-high transition of the reset signal initiates a reset sequence, as described in the reset operation section of this data sheet. in software mode, two additional power-down controls are provided. the pdn12 and pdn34 bits are located in control register 6 and may be used to power-down channel pairs, with pdn12 corresponding to channels 1 and 2, and pdn34 corresponding to channels 3 and 4. this allows the user to conserve power when a channel pair is not in use. the power-down function is the same as described in the previous paragraph for the corresponding channel pair. unlike the power-down function implemented using the rst input, setting a power-down bit will immediately power down the corresponding channel pair. when exiting power-down mode, either by forcing the rst input high or by setting the pdn12 or pdn34 bits low, the analog outputs will transition from the high-impedance state to the mute state, with the output level set to the bipolar zero voltage. there may be a small transient created by this transition, since internal capacitor charge can initially force the output to a voltage above or below bipolar zero, or external circuitry can pull the outputs to some other voltage level. figure 8 illustrates the state of the analog outputs before, during, and after a power-down event. 18 submit documentation feedback www.ti.com 1024 system clock periods required for initialization scki internal reset 0v 0v 0v t rstl > 40ns rst internal reset analog outputs outputs are on outputs are muted for 1024 scki periods outputs are on outputs are muted initialization period hi lo
audio serial port pcm4104-ep sbas419 ? june 2007 figure 8. analog output state for power-down operations the audio serial port provides a common interface to digital signal processors, digital interface receivers (aes3, s/pdif), and other digital audio devices. the port operates as a slave to the processor, receiver, or other clock generation circuitry. figure 9 illustrates a typical audio serial port connection to a processor or receiver. the audio serial port is comprised of four signal pins: bck (pin 15), lrck (pin 16), data0 (pin 17), and data1 (pin 18). figure 9. audio serial port connections for left justified, right justified, and i 2 s formats 19 submit documentation feedback www.ti.com analog outputs 65,536 scki periods outputs are on outputs are muted rst 0v v dd analog outputs 1024 scki periods required for initialization 1024 scki periods required for initialization outputs are on outputs are on outputs are on outputs are high impedance outputs are high impedance outputs transition from high impedance to muted state outputs transition from high impedance to muted state pdn12 pdn34 lo hi outputs are on transitioning to driven state lrck bck data0 data1 fsx clkx dx0 dx1 system clock pcm4104 dsp scki
pcm4104-ep sbas419 ? june 2007 the lrck pin functions as either the left/right word clock or the frame synchronization clock, depending upon the data format selected. the lrck frequency is equal to the input sampling frequency (44.1 khz, 48 khz, 96 khz, etc.). the bck pin functions as the serial data clock input. this input is referred to as the bit clock. the bit clock runs at an integer multiple of the input sampling frequency. typical multiples include 32, 48, 64, 96, 128, 192, and 256, depending upon the data format, word length, and system clock frequency selected. the data0 and data1 pins are the audio data inputs. when using left justified, right justified, or i 2 s data formats, the data0 pin carries the audio data for channels 1 and 2, while the data1 pin carries the audio data for channels 3 and 4. when using tdm data formats, data0 carries the audio data for all four channels, while the data1 input is ignored. the audio serial port data formats are shown in figure 10 , figure 13 , and figure 14 . data formats are selected by using the fmt[2:0] bits in control register 7 in software mode, or by using the fmt0 (pin 25), fmt1 (pin 26), and fmt2 (pin 27) inputs in standalone mode. in software mode, the user may also select the phase (normal or inverted) for the lrck input, as well as the data sampling edge for the bck input (either rising or falling edge). the reset default conditions for the software mode are normal phase for lrck and rising edge data sampling for bck. the left justified, right justified, and i 2 s data formats are similar to one another, with differences in data justification and word length. the pcm audio data must be two's complement binary, msb first. figure 10 provides illustrations for these data formats. the tdm formats carry the information for four or eight channels on a single data line. the data0 input (pin 17) is used as the data input for the tdm formats. the data is carried in a time division multiplexed fashion; hence, the tdm acronym used to describe this format. figure 12 shows the tdm connection of two pcm4104 devices. the data for each channel is assigned one of the time slots in the tdm frame, as shown in figure 13 and figure 14 . the sub-frame assignment for each pcm4104 is determined by the state of the sub input (pin 13). when sub is forced low, the device is assigned to sub-frame 0. when sub is forced high, the device is assigned to sub-frame 1. figure 10. left justified, right justified, and i 2 s data formats 20 submit documentation feedback www.ti.com msb lsb msb lsb m s b lsb msb lsb lsb msb lsb msb lrck bck data0 data1 lrck bck data0 data1 lrck bck data0 data1 (a) left?justified data format (b) right?justified data format (c) i 2 s data format 1/f s ch. 1 (data0) or ch. 3 (data1) ch. 2 (data0) or ch. 4 (data1)
pcm4104-ep sbas419 ? june 2007 figure 11. audio serial port timing for left justified, right justified, and i 2 s data formats 21 submit documentation feedback www.ti.com lrck bck (bcke = 0) data0 data1 t ds t dh t bklrd bck (bcke = 1) t lrbkd t bckp t bckhl pa r a m e ter d es c r ip t io n m in m a x u n its 70 ns 30 ns 10 ns 10 ns 10 ns 10 ns 50 % bck cycle time bck high/low time lrck edge to bck sampling edge delay bck sampling edge to lrck edge delay data setup time data hold time lrck duty cycle t bckp t bckhl t lrbkd t bklrd t ds t dh -
pcm4104-ep sbas419 ? june 2007 figure 12. tdm connection figure 13. tdm data formats: long frame 22 submit documentation feedback www.ti.com system clock sub sub pcm4104 pcm4104 device #1 (sub?frame 0) device #2 (sub?frame 1) scki v cc fsx clkx dx lrck bck data0 lrck bck data0 dsp scki lrck normal, zero bck delay lrck normal, one bck delay lrck inverted, zero bck delay lrck inverted, one bck delay data0 supports 8 channels, or two pcm4104 devices. slot 1 slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 ch. 1 ch. 2 ch. 3 ch. 4 ch. 1 ch. 2 ch. 3 ch. 4 sub?frame 0 (sub = 0) sub?frame 1 (sub = 1) one frame bck = 192f s or 256f s in the case of bck = 192f s , each time slot is 24 bits long and contains the 24?bit audio d ata for the corresponding channel. in the case of bck = 256f s , each time slot is 32 bits long and contains the 24?bit audio d ata for the corresponding channel. the audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don ' t care bits. audio data is always presented in two's complement, msb?fir st format. tdm data formats - long frame supported for single and dual rate sampling modes only
pcm4104-ep sbas419 ? june 2007 figure 14. tdm data formats: short frame figure 15. tdm timing 23 submit documentation feedback www.ti.com slot 1 slot 2 slot 3 slot 4 ch. 1 ch. 2 ch. 3 ch. 4 in the case of bck = 96f s , each time slot is 24 bits long and contains the 24?bit audio d ata for the corresponding channel. in the case of bck = 128f s , each time slot is 32 bits long and contains the 24?bit audio d ata for the corresponding channel. the audio data is left justified in the time slot, with the the least significant 8 bits of each time slot being don ' t care bits. audio data is always presented in two's complement, msb?fir st format. lrck normal, zero bck delay lrck normal, one bck delay lrck inverted, zero bck delay lrck inverted, one bck delay data0 supports 4 channels, or one pcm4104 device. one frame bck = 96f s or 128f s (the sub pin is ignored when using a short frame) tdm data formats - short frame all sampling modes supported lrck bck (bcke = 0) data0 t ds t dh t lrbkd t lrckp t bnf t bkbf one frame bck (bcke = 1) pa r a m e t er d e sc r ipt io n m in m a x u n it s 1/f bck 1/f bck 12 10 10 12 ns ns ns ns ns ns t lrckp t lrbkd t ds t dh t bnf t bkbf lrck pulse width lrck active edge to bck sampling edge delay data setup time data hold time lrck transition before new frame bck sampling edge to new frame delay
standalone mode configuration sampling mode audio data format soft mute function pcm4104-ep sbas419 ? june 2007 standalone mode is selected by forcing the mode input (pin 8) low. standalone mode operation provides a subset of the functions available in software mode, while providing an option for a simplified control model. standalone configuration is accomplished by either hardwiring or driving a small set of input pins with external logic or switches. standalone mode functions include sampling mode and audio data format selection, an all-channel soft mute function, and digital de-emphasis filtering. the following paragraphs provide a brief description of each function available when using standalone mode. the sampling mode is selected using the fs0 (pin 28) and fs1 (pin 29) inputs. a more detailed discussion of the sampling modes was provided in an earlier section of this data sheet. table 2 summarizes the sampling mode configuration for standalone mode. table 2. sampling mode configuration fs1 fs0 sampling mode 0 0 single rate 0 1 dual rate 1 0 quad rate 1 1 - not used - the audio data format is selected using the fmt0 (pin 25), fmt1 (pin 26), and fmt2 (pin 27) inputs. a detailed discussion of the audio serial port operation and the corresponding data formats was provided in the audio serial port section on page 19. for standalone mode, the lrck polarity is always normal, while the serial audio data is always sampled on the rising edge of the bck clock. table 3 shows the audio data format configuration for standalone mode. table 3. audio data format configuration fmt2 fmt1 fmt0 audio data format 0 0 0 24-bit left justified 0 0 1 24-bit i2s 0 1 0 tdm with zero bck delay 0 1 1 tdm with one bck delay 1 0 0 24-bit right justified 1 0 1 20-bit right justified 1 1 0 18-bit right justified 1 1 1 16-bit right justified the mute input (pin 10) may be used in either the standalone or software modes to simultaneously mute the four output channels. the soft mute function slowly ramps the digital output attenuation from its current setting to the mute level, minimizing or eliminating audible artifacts. table 4 summarizes mute function operation. table 4. mute function configuration mute analog outputs 0 on (mute disabled) 1 muted 24 submit documentation feedback www.ti.com
digital de-emphasis software mode configuration digital attenuation digital de-emphasis soft mute zero data mute pcm4104-ep sbas419 ? june 2007 this is a global digital function (common to all four channels) and provides de-emphasis of the higher frequency content within the 20-khz audio band. de-emphasis is required when the input audio data has been pre-emphasized. pre-emphasis entails increasing the amplitude of the higher frequency components in the 20-khz audio band using a standardized filter function in order to enhance the high-frequency response. the pcm4104 de-emphasis filters implement the standard 50/15 s de-emphasis transfer function commonly used in digital audio applications. de-emphasis filtering is available for three input sampling frequencies in single rate sampling mode: 32 khz, 44.1 khz, and 48 khz. de-emphasis is not available when operating in dual or quad rate sampling modes. the de-emphasis filter is selected using the dem0 (pin 12) and dem1 (pin 11) inputs. table 5 illustrates the de-emphasis filter configuration for standalone mode. table 5. digital de-emphasis configuration dem1 dem0 digital de-emphasis mode 0 0 off (de-emphasis disabled) 0 1 48 khz 1 0 44.1 khz 1 1 32 khz software mode is selected by forcing the mode input(pin 8) high. software mode operation provides full access to the features of the pcm4104 by allowing the writing and reading of on-chip control registers. this is accomplished using the four-wire spi port. the following paragraphs provide a brief description of each function available when using software mode. the audio signal for each channel can be attenuated in the digital domain using this function. attenuation settings from 0 db (unity gain) to ?119.5 db are provided in 0.5 db steps. in addition, the attenuation level may be set to the mute state. the rate of change for the digital attenuation function is one 0.5 db step for every eight lrck periods. each channel has its own independent attenuation control, accessed using control registers 1 through 4. the reset default setting for all channels is 0 db, or unity gain (no attenuation applied). the de-emphasis function is accessed through control register 5 using the dem[1:0] bits. the reset default setting is that the de-emphasis is disabled for all four channels. de-emphasis filter operation is described in the standalone mode configuration section of this data sheet. each of the four d/a converter channels has its own independent soft mute control, located in control register 5. the reset default is normal output for all four channels with the soft mute function disabled. the mute input (pin 10) also functions in software mode, with a high input forcing soft mute on all four channels. the pcm4104 includes a zero data detection and mute function in software mode. this function automatically mutes a given channel when 1024 consecutive lrck periods of all zero data are detected for that channel. the zero data mute function is enabled and disabled using the zdm bit in control register 5. the zero data mute function is disabled by default on power up or reset. 25 submit documentation feedback www.ti.com
output phase reversal sampling mode power-down modes software reset audio data formats, lrck polarity, and bck sampling edge serial peripheral interface (spi) port operation control byte (or byte 0) pcm4104-ep sbas419 ? june 2007 the pcm4104 includes an output phase reversal function, which provides the ability to invert the output phase for all four channels, either for testing or for matching various output circuit configurations. this function is controlled using the phase bit, located within control register 5. the output phase is set to noninverted by default on power up or reset. sampling mode configuration was discussed earlier in this data sheet, with table 1 providing a reference for common sampling and system clock frequencies. the fs0 and fs1 bits located in control register 6 are used to set the sampling mode. the sampling mode defaults to single rate on power up or reset. the power-down control bits are located in control register 6. these bits are used to power down pairs of d/a converters within the pcm4104. the pdn12 bit is used to power down channels 1 and 2, while the pdn34 bit is used to power down channels 3 and 4. when a channel pair is powered down, it ignores the audio data inputs and sets its outputs to a high-impedance state. by default, the power-down bits are disabled on power up or reset. this reset function allows a reset sequence to be initiated under software control. all control registers are reset to their default state. the reset bit, rst, is located in control register 6. setting this bit to 1 initiates a one-time reset sequence. the rst bit is cleared by the initialization sequence. control register 7 is used to configure the pcm4104 audio serial port. audio serial port operation was discussed previously in this data sheet; refer to that section for more details regarding the functions controlled by this register. the control register definitions provide additional information regarding the register functions and their default settings. the spi port is a four-wire synchronous serial interface that is used to access the on-chip control registers when the pcm4104 is configured for software mode operation. the cdin input (pin 23) is the serial data input for the port, while cdout (pin 24) is used for reading back control register contents in a serial fashion. the cs input (pin 21) functions as the chip select input, and must be forced low for register write or read access. the cclk input (pin 22) functions as the serial data clock, used to clock data in and out of the port. data is clocked into the port on the rising edge of cclk, while data is clocked out of the port on the falling edge of cclk. there are three modes of operation supported for the spi port: single register, continuous, and auto-increment. the single register and continuous modes are similar to one another. in continuous mode, instead of bringing the cs input high after writing or reading a single register, the cs input is held low and a new control byte is issued with a new address for the next write or read operation. continuous mode allows multiple, sequential or nonsequential register addresses to be read or written in succession, as shown in figure 16 . auto-increment mode is designed for writing or reading multiple sequential register addresses. after the first register is written or read, the register address is automatically incremented by 1, so the next write or read operation is performed without issuing another control byte, as shown in figure 17 . the control byte, or byte 0, is the first byte written to the pcm4104 spi port when performing a write or read operation. the control byte includes bits that define the operation to be performed (read or write), the auto-increment mode status, and the control register address. the read/write bit, r/ w, is set to 0 to indicate a register write operation, or set to 1 for a register read operation. 26 submit documentation feedback www.ti.com
pcm4104-ep sbas419 ? june 2007 the increment bit, inc, enables or disables the auto-increment mode of operation. when this bit is set to a 0, auto-increment operation is disabled, and the operation performed is either single register or continuous. setting the inc bit to 1 enables auto-increment operation. a two-bit key code, 10 b , follows the inc bit and must be present in order for any operation to take place on the control port. any other combination for these bits will result in the port ignoring the write or read request. the four-bit address field, a[3:0], is used to specify the control register address for the read or write operation, or the starting address for an auto-increment write or read operation. figure 16. single register and continuous write or read operation 27 submit documentation feedback www.ti.com cs cdin cclk set cs = 1 here for single register operations keep cs = 0 for writing or reading multiple registers in conti nuous mode byte 0 byte 1 byte 0 byte 1 byte n auto ?increment control: set to 0 for single register or cont inuous operation read/writecontrol: 0 = write 1 = read register data control byte register data control byte cdout high impedance byte 1 high impedance byte 2 byte n register data register data r/w inc 1 0 a3 a2 a1 a0 register address msb lsb control byte definition (byte 0)
pcm4104-ep sbas419 ? june 2007 figure 17. auto-increment write or read operation figure 18. spi port timing 28 submit documentation feedback www.ti.com cs cdin cclk keep cs = 0 for auto?increment operation byte 0 byte 1 byte 2 byte 3 byte n r/w inc 1 0 a3 a2 a1 a0 auto?increment control: set to 1 for auto?increment operat ion read/writecontrol: 0 = write 1 = read msb lsb control byte definition (byte 0) register data control byte cdout high impedance byte 1 byte 2 byte 3 byte n register data register address high impedance (hi z) hi z cclk cdin cdout msb msb lsb t do t ds t dh t ch t csz parameter description min max unit cdin data setup time 52 2 55 ns cdin data hold time ns hold time ns cdout data delay time ns high to cdout hi z t ds t dh t ch t do t csz ns cs cs cs
control register definitions (software mode only) register 1: attenuation control register ? channel 1 register 2: attenuation control register ? channel 2 register 3: attenuation control register ? channel 3 pcm4104-ep sbas419 ? june 2007 the pcm4104 includes a small set of control registers, which are utilized to configure the full set of on-chip functions in software mode. the register map is shown in table 6 . register 0 is reserved for factory use and should not be written to for normal operation. register 0 defaults to all zero data on power up or reset. table 6. control register map control register msb lsb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 address bit 7 bit 0 (hex) 0 0 0 0 0 0 0 0 0 1 at17 at16 at15 at14 at13 at12 at11 at10 2 at27 at26 at25 at24 at23 at22 at21 at20 3 at37 at36 at35 at34 at33 at32 at31 at30 4 at47 at46 at45 at44 at43 at42 at41 at40 5 mut4 mut3 mut2 mut1 zdm phase dem1 dem0 6 rst 0 0 0 pdn34 pdn12 fs1 fs0 7 0 0 bcke lrckp 0 fmt2 fmt1 fmt0 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at17 at16 at15 at14 at13 at12 at11 at10 this register controls the digital output attenuation for channel 1. default: at1[7:0] = 255, or 0 db let n = at1[7:0]. for n = 16 to 255, attenuation (db) = 0.5 (255 ? n) or n = 0 to 15, attenuation (db) = infinite (muted) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at27 at26 at25 at24 at23 at22 at21 at20 this register controls the digital output attenuation for channel 2. default: at2[7:0] = 255, or 0 db let n = at2[7:0]. for n = 16 to 255, attenuation (db) = 0.5 (255 ? n) or n = 0 to 15, attenuation (db) = infinite (muted) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at37 at36 at35 at34 at33 at32 at31 at30 this register controls the digital output attenuation for channel 3. default: at3[7:0] = 255, or 0 db let n = at3[7:0]. for n = 16 to 255, attenuation (db) = 0.5 (255 ? n) or n = 0 to 15, attenuation (db) = infinite (muted) 29 submit documentation feedback www.ti.com
register 4: attenuation control register ? channel 4 register 5: function control register dem[1:0] ? digital de-emphasis phase ? output phase zdm ? zero data mute mut[4:1] ? soft mute pcm4104-ep sbas419 ? june 2007 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) at47 at46 at45 at44 at43 at42 at41 at40 this register controls the digital output attenuation for channel 4. default: at4[7:0] = 255, or 0 db let n = at4[7:0]. for n = 16 to 255, attenuation (db) = 0.5 (255 ? n) or n = 0 to 15, attenuation (db) = infinite (muted) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) mut4 mut3 mut2 mut1 zdm phase dem1 dem0 this register controls various d/a converter functions, including de-emphasis filtering, output phase reversal, zero data mute, and per-channel soft muting. de-emphasis is available for single rate mode only. de-emphasis is disabled for dual and quad rate modes. dem1 dem0 de-emphasis selection 0 0 de-emphasis disabled (default) 0 1 de-emphasis for f s = 48 khz 1 0 de-emphasis for f s = 44.1 khz 1 1 de-emphasis for f s = 32 khz phase output phase 0 noninverted (default) 1 inverted zdm zero mute 0 disabled (default) 1 enabled mutx d/a converter output 0 on (default) 1 muted note: x = channel number. 30 submit documentation feedback www.ti.com
register 6: system control register fs[1:0] ? sampling mode pdn12 ? power-down for channels 1 and 2 pdn34 ? power-down for channels 3 and 4 rst ? software reset (value defaults to 0) pcm4104-ep sbas419 ? june 2007 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rst 0 0 0 pdn34 pdn12 fs1 fs0 this register controls various system level functions of the pcm4104, including sampling mode, power down, and soft reset. fs1 fs0 sampling mode 0 0 single rate (default) 0 1 dual rate 1 0 quad rate 1 1 - not used - pdn12 power down for channels 1 and 2 0 disabled (default) 1 enabled pdn34 power down for channels 3 and 4 0 disabled (default) 1 enabled setting this bit to 1 will initiate a logic reset of the pcm4104. this bit functions the same as an external reset applied at the rst input (pin 9). 31 submit documentation feedback www.ti.com
register 7: audio serial port control register fmt[2:0] ? audio data format pcm4104-ep sbas419 ? june 2007 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 0 0 bcke lrckp 0 fmt2 fmt1 fmt0 this register is used to control the data format and clock polarity for the pcm4104 audio serial port. fmt2 fmt1 dem0 data format 0 0 0 24-bit left justified (default) 0 0 1 24-bit i 2 s 0 1 0 tdm with zero bck delay 0 1 1 tdm with one bck delay 1 0 0 24-bit right justified 1 0 1 20-bit right justified 1 1 0 18-bit right justified 1 1 1 16-bit right justified lrckp ? lrck polarity (0 = normal, 1 = inverted). defaults to 0. bcke ? bck sampling edge (0 = rising edge, 1 = falling edge), defaults to 0. 32 submit documentation feedback www.ti.com
application information basic circuit configurations analog output filter circuits pcm4104-ep sbas419 ? june 2007 this section provides practical information for system and hardware engineers that are designing in the pcm4104. figure 19 and figure 20 show typical circuit configurations for the pcm4104 operated in standalone and software modes. power supply bypass and reference decoupling capacitors should be placed as close to the corresponding pcm4104 pins as possible. a common ground is shown in both figures, with the analog and digital ground pins connected to a common plane. separate power supplies are utilized for the analog and digital sections, with 5 v required for the pcm4104 analog supplies and 3.3 v required for the digital supply. the 5 v analog supply may be derived from a higher valued, positive analog power supply using a linear voltage regulator, such as the reg103 available from texas instruments. the 3.3 v digital supply can be derived from a primary 5 v digital supply using a linear voltage regulator, such as the reg1117, also from ti. the pcm4104evm evaluation module provides an example of how the common ground with separate supply approach can be successfully implemented. the pcm4104evm user's guide includes schematics and pcb layout plots for reference. the evaluation module is available through texas instruments' distributors and sales representatives, or may be ordered online through the ti estore, which can be accessed through the ti home page at http://www.ti.com. the master clock generator supplies the system clock for the pcm4104, as well as the audio data source, such as a digital signal processor. the lrck and bck audio clocks should be derived from the system clock, in order to ensure synchronous operation. an external output filter is recommended for each differential output pair. the external output filter further reduces the out-of-band noise energy produced by the delta-sigma modulator, while providing band limiting suitable for audio reproduction. a 2nd-order butterworth low-pass filter circuit with a ?3 db corner frequency from 50 khz to 180 khz is recommended. the configuration of the output filter circuit is dependent upon whether a single-ended or differential output is required. single-ended outputs are commonly used in consumer playback systems, while differential or balanced outputs are used in many professional audio applications, such as recording or broadcast studios and live sound systems. figure 21 illustrates an active filter circuit that uses a single op amp to provide both 2nd-order low-pass filtering and differential to single-ended signal conversion. this circuit is used on the pcm4104evm evaluation circuit and meets the published typical electrical characteristics for dynamic performance. the single-ended output is convenient for connecting to both headphone and power amplifiers when used for listening tests. the quality of the op amp used is this circuit is important, as many devices will degrade the dynamic range and/or total harmonic distortion plus noise (thd+n) specifications for the pcm4104. an ne5534a is shown in figure 21 and provides both low noise and distortion. bipolar input op amps with equivalent specifications should produce similar measurement results. devices that exhibit higher equivalent input noise voltage, such as the texas instruments opa134 or opa604 families, will produce lower dynamic range measurements (approximately 1 db to 2 db lower than the typical pcm4104 specification), while having little or no impact on the thd+n specification when measuring a full-scale output level. figure 22 illustrates a fully-differential output filter circuit suitable for use with the pcm4104. the opa1632 from texas instruments provides the fully differential signal path in this circuit. the opa1632 features very low noise and distortion, making it suitable for high-end audio applications. texas instruments provides a free software tool, filterprot, used to assist in the design of active filter circuits. the software supports design of multiple feedback (mfb), sallen-key, and fully differential filter circuits. filterpro is available from the ti web site. additionally, ti document number sbaf001a, also available from the ti web site, provides pertinent application information regarding the proper usage of the filterpro program. 33 submit documentation feedback www.ti.com
pcm4104-ep sbas419 ? june 2007 application information (continued) figure 19. typical standalone mode configuration 34 submit documentation feedback www.ti.com 36 35 34 33 32 31 30 29 28 27 26 25 v out 4+ v out 4 - agnd2 v ref 4 - v ref 4+ nc nc fs1 fs0 fmt2 fmt1 fmt0 v com 1 v out 2+ v out 2 - v cc 1 v ref 2+ v ref 2 - v ref 3 - v ref 3+ v cc 2 v out 3 - v out 3+ v com 2 sub scki bck lrck data0 data1 v dd dgnd cs cclk cdin cdout 12 3 4 5 6 7 8 9 10 11 12 v out 1+ v out 1 - agnd1 v ref 1 - v ref 1+ nc nc mode rst mute dem1 dem0 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 pcm4104 audio data source master clock generator from logic, m p, or dsp from logic, m p, or dsp to analog output filters (1) (2) (2) 0.1 m f 10 m f +5.0v pin 40 pin 45 + 0.1 m f 10 m f + (2) +3.3v pin 19 0.1 m f 10 m f + (1) refer to and in this document. (2) refer to in this document for external connection requir ements. no t ag no t ag no t ag
pcm4104-ep sbas419 ? june 2007 application information (continued) figure 20. typical software mode configuration 35 submit documentation feedback www.ti.com 36 35 34 33 32 31 30 29 28 27 26 25 v out 4+ v out 4 - agnd2 v ref 4 - v ref 4+ nc nc fs1 fs0 fmt2 fmt1 fmt0 v com 1 v out 2+ v out 2 - v cc 1 v ref 2+ v ref 2 - v ref 3 - v ref 3+ v cc 2 v out 3 - v out 3+ v com 2 sub scki bck lrck data0 data1 v dd dgnd cs cclk cdin cdout 12 3 4 5 6 7 8 9 10 11 12 v out 1+ v out 1 - agnd1 v ref 1 - v ref 1+ nc nc mode rst mute dem1 dem0 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 pcm4104 audio data source master clock generator from logic or host control to analog output filters (1) (2) (2) 0.1 m f 10 m f +5.0v pin 40 pin 45 + 0.1 m f 10 m f + host control (2) +3.3v +3.3v pin 19 0.1 m f 10 m f + (1) refer to and in this document. (2) refer to in this document for external connection requir ements. no t ag no t ag no t ag
pcm4104-ep sbas419 ? june 2007 application information (continued) figure 21. single-ended output filter circuit 36 submit documentation feedback www.ti.com 499 w 604 w 1k w 100 w filtered output rca or 1/4?inch phone jack ne5534a pcm4104 560pf 100 m f 499 w 1k w 560pf 604 w 100 m f 2200pf 22pf 0.1 m f 10 m f +12v voutn - voutn+ n = 1, 2, 3, or 4 23 7 6 4 10 m f 0.1 m f - 12v + + + +
pcm4104-ep sbas419 ? june 2007 application information (continued) figure 22. differential output filter circuit 37 submit documentation feedback www.ti.com 499 w 604 w 100 w 100 w 1k w 1k w filtered output male xlr connector opa1632 pcm4104 560pf 560pf 100 m f 499 w 604 w 100 m f 2200pf 22pf 0.1 m f 10 m f - 15v voutn - voutn+ n = 1, 2, 3, or 4 2 1 8 en v ocm 2 3 1 7 63 4 5 0.1 m f 10 m f +15v + + + +
package option addendum www.ti.com 31-may-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pcm4104ipfbrep active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 pcm4104ep v62/07643-01xe active tqfp pfb 48 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 pcm4104ep (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 31-may-2014 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of pcm4104-ep : ? catalog: pcm4104 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant pcm4104ipfbrep tqfp pfb 48 1000 330.0 16.8 9.6 9.6 1.5 12.0 16.0 q2 package materials information www.ti.com 26-jan-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) pcm4104ipfbrep tqfp pfb 48 1000 367.0 367.0 38.0 package materials information www.ti.com 26-jan-2013 pack materials-page 2
mechanical data mtqf019a january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 pfb (s-pqfp-g48) plastic quad flatpack 4073176 / b 10/96 gage plane 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 0,17 0,27 24 25 13 12 sq 36 37 7,20 6,80 48 1 5,50 typ sq 8,80 9,20 1,05 0,95 1,20 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2014, texas instruments incorporated

▲Up To Search▲

Price & Availability of PCM4104-EP-15

	To Download PCM4104-EP-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .